1. Technical Field
The present invention relates in general to the field of logic design testing, and in particular to the accurately defined logic areas in the logic design. Still more particularly, the present invention relates to a method and system for associating specific logic areas with specific tests, such that a change in the specific logic area or a change in the test will require re-testing only affected logic areas.
2. Description of the Related Art
Building computer logic takes many steps before the computer logic is physically manufactured. The logic designer typically uses synthesis tools, known as Hardware Descriptor Languages (HDLs), to describe, design and document electronic circuits, as well as simulating faults, in software simulations of hardware. Examples of HDLs are VERILOG® and VHDL (Very-high-speed-integrated-circuit Hardware Descriptor Language) for Very Large Scale Integrated Circuits (VLSICs); and Register Transfer Language (RTL) to describe registers in computer logic and the way that data is transferred between such registers. By including a description of interfaces for logic and the logic's behavior, HDLs simulate physical hardware to such an extent that a virtual machine can be constructed in software alone. Such virtual machines are made up of multiple Finite State Machines (FSMs), also referred to as function areas or logic areas. Examples of FSMs are error correction logic, arbitration units, flow-control management units for determining if packets can be sent, etc.
After being constructed in software, the virtual machine is tested using an Architecture Verification Program (AVP), which is a test-case format that specifies an initial input and expected output of the virtual machine. The AVP is made up of multiple testcases, each of which affect one or more FSMs. Although an AVP may be useful in determining if an entire virtual machine is working, erroneous outputs from the virtual machine alone do not identify which FSM or FSMs are responsible for the failure. While documentation comments in the AVP may attempt to identify affected FSMs and thus the source of the failure, such predictions are rarely complete due to unexpected consequences of test software on FSM architecture, as well as unexpected anomalies in the FSM architecture itself. Thus, upon a test failure, the tester of the virtual machine must modify the FSMs predicted by the AVP programmer to be affected by the AVP, and then the entire AVP is re-run. Such a process is very time consuming, as a full AVP may take days to run, making such a process inefficient.
What is needed, therefore, is a method of accurately identifying which FSMs are affected by a testcase. This would allow an engineer to adjust/correct only FSMs affected by a failed testcase. Such a method also would allow the engineer to make changes to the virtual machine, followed by re-testing of only affected FSMs, thus reducing the time to re-test the newly modified virtual machine.